Huy Nam Nguyen

According to our database, Huy Nam Nguyen authored at least 14 papers between 1988 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

An QoS Aware Mapping of Cores Onto NoC Architectures.

Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi

Proceedings of the Parallel and Distributed Processing and Applications, 2007

2006

The Optimum Network on Chip Architectures for Video Object Plane Decoder Design.

Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi

Proceedings of the Parallel and Distributed Processing and Applications, 2006

Throughput Aware Mapping for Network on Chip Design of H.264 Decoder.

Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi

Proceedings of the Frontiers of High Performance Computing and Networking, 2006

2005

Realization of Video Object Plane Decoder on On-Chip Network Architecture.

Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Designing On-Chip Network Based on Optimal Latency Criteria.

Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi

Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Realization of video object plane decoder on mesh on-chip network architecture.

Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi

Proceedings of the Third IASTED International Conference on Circuits, 2005

Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design.

Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi

Proceedings of the Embedded and Ubiquitous Computing, 2005

1996

Design Verification based on Hardware Emulation.

Huy Nam Nguyen, Michel Thill

Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

1995

Application of synthesis to support hardware emulation.

Huy Nam Nguyen, Yvon Gressus, Michel D'Hoe

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

Auriga2: a 4.7 million-transistor CISC microprocessor.

J. P. Tual, Michel Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

The Structured Logic CAD Suite Used on the DPS7000 System.

Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Logic Synthesis and Verification of the CPU and Caches of a Mainframe System.

Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1989

Automated synthesis of combinational logic using problem solving techniques.

Huy Nam Nguyen, L. Ducousso

Proceedings of the SPLT'89, 1989

1988

Utilisation de CHIP pour la synthèse et vérification des circuits CMOS.

Huy Nam Nguyen, L. Ducousso

Proceedings of the SPLT'88, 1988