Huong Ho

According to our database, Huong Ho authored at least 6 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.

Marc-Andre LaCroix, Euhan Chong, Weilun Shen, Ehud Nir, Faisal Ahmed Musa, Haitao Mei, Mohammad-Mahdi Mohsenpour, Semyon Lebedev, Babak Zamanlooy, Carlos Carvalho, Qian Xin, Dmitry Petrov, Henry Wong, Huong Ho, Yang Xu, Sina Naderi Shahi, Peter Krotnev, Chris Feist, Howard Huang, Davide Tonietto

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.

Marc-Andre LaCroix, Henry Wong, Yun Hua Liu, Huong Ho, Semyon Lebedev, Petar Krotnev, Dorin Alexandru Nicolescu, Dmitry Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, Faisal Ahmed Musa, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2014

Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m).

Huong Ho

J. Signal Process. Syst., 2014

2011

A high performance hardware architecture for multi-frame hierarchical motion estimation.

Huong Ho, Robert Klepko, Nam Ninh, Demin Wang

IEEE Trans. Consumer Electron., 2011

2010

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

J. Signal Process. Syst., 2010

2009

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications.

Huong Ho, Valek Szwarc, Tad A. Kwasniewski

Int. J. Reconfigurable Comput., 2009