Hung-Yu Li

According to our database, Hung-Yu Li authored at least 6 papers between 2000 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder.

Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.

Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2006

An AND-type match-line scheme for high-performance energy-efficient content addressable memories.

Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh

IEEE J. Solid State Circuits, 2006

2005

Design techniques for single-low-V_DD CMOS systems.

Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen

IEEE J. Solid State Circuits, 2005

2003

Energy Efficient Caching-on-Cache Architectures for Embedded Systems.

Hung-Cheng Wu, Tien-Fu Chen, Hung-Yu Li, Jinn-Shyan Wang

J. Inf. Sci. Eng., 2003

2000

Low-power embedded SRAM with the current-mode write technique.

Jinn-Shyan Wang, Wayne Tseng, Hung-Yu Li

IEEE J. Solid State Circuits, 2000