Hung-Yi Kuo

According to our database, Hung-Yi Kuo authored at least 4 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.

Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.

Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2016

Software-Defined Network Virtualization Platform for Enterprise Network Resource Management.

Jiann-Liang Chen, Yi-Wei Ma, Hung-Yi Kuo, Chu-Sing Yang, Wen-Chien Hung

IEEE Trans. Emerg. Top. Comput., 2016

A 0.034mm², 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016