Hung-Yi Huang
Orcid: 0000-0002-1465-9995
According to our database1,
Hung-Yi Huang
authored at least 7 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
A 14b 16GS/s Time-Interleaving Oirect-RF Synthesis OAe with T-OEM Achieving -70dBc IM3 up to 7.8GHz in 7nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2021
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone.
IEEE J. Solid State Circuits, 2021
2020
A 0.07-mm<sup>2</sup> 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing.
IEEE J. Solid State Circuits, 2020
A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 0.07mm<sup>2</sup> 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2014
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique.
IEEE J. Solid State Circuits, 2014