Hung-Ming Chen

Orcid: 0000-0001-8173-3131

According to our database1, Hung-Ming Chen authored at least 170 papers between 1996 and 2024.

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Bibliography

2024
One Raman DTS Interrogator Channel Supports a Dual Separate Path to Realize Spatial Duplexing.
Sensors, August, 2024

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm<sup>2</sup>) Single-Crystalline Si on SiO2 by Elevated-Epi.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

ML/DL-Based Signal Integrity Optimization for InFO Routing.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Enabling System Design in 3D Integration: Technologies and Methodologies.
Proceedings of the 2024 International Symposium on Physical Design, 2024

A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
On Reducing LDE Variations in Modern Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Layout Synthesis of Analog Primitive Cells with Variational Autoencoder.
Proceedings of the 19th International Conference on Synthesis, 2023

On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Reshaping System Design in 3D Integration: Perspectives and Challenges.
Proceedings of the 2023 International Symposium on Physical Design, 2023

DPRoute: Deep Learning Framework for Package Routing.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Deep Learning Model for Dynamic Hand Gesture Recognition for Natural Human-Machine Interface on End Devices.
Int. J. Inf. Syst. Model. Des., 2022

Innovative service model of information services based on the sustainability balanced scorecard: Applied integration of the fuzzy Delphi method, Kano model, and TRIZ.
Expert Syst. Appl., 2022

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

On Optimizing Capacitor Array Design for Advanced Node SAR ADC.
Proceedings of the 18th International Conference on Synthesis, 2022

Red-black tree I/O management of solid state disk with elastic striping design.
Proceedings of the Conference on Research in Adaptive and Convergent Systems, 2022

An OpenDDS cross-platform data exchange module for cloud-edge-based industrial internet of things.
Proceedings of the Conference on Research in Adaptive and Convergent Systems, 2022

Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM.
Proceedings of the 19th International SoC Design Conference, 2022

Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator.
Proceedings of the 19th International SoC Design Conference, 2022

DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Practical Substrate Design Considering Symmetrical and Shielding Routes.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA).
ACM J. Emerg. Technol. Comput. Syst., 2021

An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Learning Based Placement Refinement to Reduce DRC Short Violations.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

On Reconfiguring Memory-Centric AI Edge Devices for CIM.
Proceedings of the 18th International SoC Design Conference, 2021

2020
Wire Load Oriented Analog Routing with Matching Constraints.
ACM Trans. Design Autom. Electr. Syst., 2020

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Understanding user acceptance of blockchain-based smart locker.
Electron. Libr., 2020

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A Three-Factor Mutual Authentication Scheme for Cyber-Physical Systems.
Proceedings of the RACS '20: International Conference on Research in Adaptive and Convergent Systems, 2020

Enhanced Privacy with Blockchain-based Storage for Data Sharing.
Proceedings of the RACS '20: International Conference on Research in Adaptive and Convergent Systems, 2020

Timing Driven Partition for Multi-FPGA Systems with TDM Awareness.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Achieving Analog Layout Integrity through Learning and Migration Invited Talk.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips.
Microelectron. J., 2019

A Structure-Based Methodology for Analog Layout Generation.
Proceedings of the 16th International Conference on Synthesis, 2019

Container-based load balancing for WebRTC applications.
Proceedings of the Conference on Research in Adaptive and Convergent Systems, 2019

More Effective Power Network Prototyping by Analytical and Centroid Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines.
Proceedings of the International Conference on Computer-Aided Design, 2019

An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2018

Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips.
ACM J. Emerg. Technol. Comput. Syst., 2018

A Multi-Fidelity Model Approach for Simultaneous Scheduling of Machines and Vehicles in Flexible Manufacturing Systems.
Asia Pac. J. Oper. Res., 2018

A learning-based methodology for routability prediction in placement.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts.
Proceedings of the 15th International Conference on Synthesis, 2018

A mutual authentication scheme with user anonymity for cyber-physical and internet of things.
Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018

Extending ML-OARSMT to net open locator with efficient and effective boolean operations.
Proceedings of the International Conference on Computer-Aided Design, 2018

Analog placement with current flow and symmetry constraints using PCP-SP.
Proceedings of the 55th Annual Design Automation Conference, 2018

Multi-level droplet routing in active-matrix based digital-microfluidic biochips.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Performance-preserved analog routing methodology via wire load reduction.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Generation of PUF-Keys on FPGAs by K-means Frequency Clustering.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Using nanoindentation to investigate the temperature cycling of Sn-37Pb solders.
Microelectron. Reliab., 2017

An analytical placer for heterogeneous FPGAs via rough-placed packing.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Designing A Simple Storage Services (S3) Compatible System Based on Ceph Software-Defined Storage System.
Proceedings of the 2nd International Conference on Multimedia Systems and Signal Processing, 2017

On reliability hardening in cyber-physical digital-microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Using a branch-and-bound and a genetic algorithm for a single-machine total late work scheduling problem.
Soft Comput., 2016

Design and evaluation of a cloud-based Mobile Health Information Recommendation system on wireless sensor networks.
Comput. Electr. Eng., 2016

A New Methodology for Noise Sensor Placement Based on Association Rule Mining.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Placement optimization of cyber-physical digital microfluidic biochips.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

An approach to anchoring and placing high performance custom digital designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation.
ACM Trans. Design Autom. Electr. Syst., 2014

ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Automatic image segmentation and classification based on direction texton technique for hemolytic anemia in thin blood smears.
Mach. Vis. Appl., 2014

Performance Evaluation of Continuity of Care Records (CCRs): Parsing Models in a Mobile Health Management System.
J. Medical Syst., 2014

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Usability Evaluation of a Cloud Computing Based Context-aware Healthcare System.
Proceedings of the e-Health - For Continuity of Care - Proceedings of MIE2014, the 25th European Medical Informatics Conference, Istanbul, Turkey, August 31, 2014

Improving power delivery network design by practical methodologies.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Planning and placing power clamps for effective CDM protection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Memcomputing: The cape of good hope: [Extended special session description].
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Cost-effective decap selection for beyond die power integrity.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Routability-driven bump assignment for chip-package co-design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Board- and Chip-Aware Package Wire Planning.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization.
ACM Trans. Design Autom. Electr. Syst., 2013

A study of row-based area-array I/O design planning in concurrent chip-package design flow.
ACM Trans. Design Autom. Electr. Syst., 2013

Escaped Boundary Pins Routing for High-Speed Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs.
Integr., 2013

A 3D visualized expert system for maintenance and management of existing building facilities using reliability-based method.
Expert Syst. Appl., 2013

An adaptive macroblock-mean difference based sorting scheme for fast normalized partial distortion search motion estimation.
Comput. Electr. Eng., 2013

Using MapReduce Framework for Mining Association Rules.
Proceedings of the Information Technology Convergence, 2013

On the way to practical tools for beyond die codesign and integration.
Proceedings of the International Symposium on Physical Design, 2013

Design of mobile healthcare service with health records format evaluation.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

A fuzzy thresholding early termination scheme of fast motion estimation for video coding.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2013

Efficient analog layout prototyping by layout reuse with routing preservation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design.
Proceedings of the Design, Automation and Test in Europe, 2013

Effective power network prototyping via statistical-based clustering and sequential linear programming.
Proceedings of the Design, Automation and Test in Europe, 2013

A network-flow based algorithm for power density mitigation at post-placement stage.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Dynamic guiding particle swarm optimization with embedded chaotic search for solving multidimensional problems.
Optim. Lett., 2012

An Efficient and Secure Dynamic ID-based Authentication Scheme for Telecare Medical Information Systems.
J. Medical Syst., 2012

Genetic programming for predicting aseismic abilities of school buildings.
Eng. Appl. Artif. Intell., 2012

K-means particle swarm optimization with embedded chaotic search for solving multidimensional problems.
Appl. Math. Comput., 2012

Hierarchical power network synthesis for multiple power domain designs.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

On construction low power and robust clock tree via slew budgeting.
Proceedings of the International Symposium on Physical Design, 2012

Configurable analog routing methodology via technology and design constraint unification.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Agglomerative-based flip-flop merging with signal wirelength optimization.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

On effective flip-chip routing via pseudo single redistribution layer.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A fast thermal aware placement with accurate thermal analysis based on Green function.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits.
J. Inf. Sci. Eng., 2011

A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction.
J. Inf. Sci. Eng., 2011

Aseismic ability estimation of school building using predictive data mining models.
Expert Syst. Appl., 2011

TSV-based 3D-IC placement for timing optimization.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

New Sorting Technique on Partial Distortion Search Using Two Bit-Transform for Fast Optimal Motion Estimation.
Proceedings of the First International Conference on Robot, Vision and Signal Processing, 2011

Mixed non-rectangular block packing for non-Manhattan layout architectures.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Clock planning for multi-voltage and multi-mode designs.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

The Development of Smart Assistive Technology Devices for Urinary Catheterization Monitoring.
Proceedings of the Fifth International Conference on Genetic and Evolutionary Computing, 2011

Fast analog layout prototyping for nanometer design migration.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

On routing fixed escaped boundary pins for high speed boards.
Proceedings of the Design, Automation and Test in Europe, 2011

Row-based area-array I/O design planning in concurrent chip-package design flow.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques.
IEICE Trans. Electron., 2010

Image Enlargement by Applying Coordinate Rotation and Kernel Stretching to Interpolation Kernels.
EURASIP J. Adv. Signal Process., 2010

Simultaneous voltage island generation and floorplanning.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A novel two-dimensional scan-control scheme for test-cost reduction.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Technology mapping with crosstalk noise avoidance.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2009

Buffer/flip-flop block planning for power-integrity-driven floorplanning.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A stochastic-based efficient critical area extractor on OpenAccess platform.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Effective decap insertion in area-array SoC floorplan design.
ACM Trans. Design Autom. Electr. Syst., 2008

An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.
J. Inf. Sci. Eng., 2008

Web-FEM: An internet-based finite-element analysis framework with 3D graphics and parallel computing environment.
Adv. Eng. Softw., 2008

An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
SODOCK: Swarm optimization for highly flexible protein-ligand docking.
J. Comput. Chem., 2007

Center of Mass-Based Adaptive Fast Block Motion Estimation.
EURASIP J. Image Video Process., 2007

Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor method.
Biosyst., 2007

Using power gating techniques in area-array SoC floorplan design.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A selective pattern-compression scheme for power and test-data reduction.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Markov model fuzzy-reasoning based algorithm for fast block motion estimation.
J. Vis. Commun. Image Represent., 2006

Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2006

On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Design of nearest neighbor classifiers: multi-objective approach.
Int. J. Approx. Reason., 2005

Current Calculation on VLSI Signal Interconnects.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

MeSwarm: memetic particle swarm optimization.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005

Flexible protein-ligand docking using particle swarm optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

Efficient gene selection for classification of microarray data.
Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004
Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space.
IEEE Trans. Syst. Man Cybern. Part B, 2004

Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm.
Proceedings of the PRICAI 2004: Trends in Artificial Intelligence, 2004

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Designing platform-based system power management on a smart tablet appliance.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Global Wire Bus Configuration with Minimum Delay Uncertainty.
Proceedings of the 2003 Design, 2003

Floorplanning with power supply noise avoidance.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001
Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Integrated power supply planning and floorplanning.
Proceedings of ASP-DAC 2001, 2001

1999
Integrated floorplanning and interconnect planning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1996
尋易(Csmart-Ⅱ):智慧型網路中文資訊檢索系統 (An Intelligent Chinese Information Retrieval System for the Internet) [In Chinese].
Proceedings of 9th Computational Linguistics Conference, 1996


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