Hung C. Ngo

According to our database, Hung C. Ngo authored at least 11 papers between 1998 and 2009.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2009

2008

Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies.

Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka

IEEE Trans. Very Large Scale Integr. Syst., 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.

Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2006

Limited switch dynamic logic circuits for high-speed low-power circuit design.

Wendy Belluomini, Damir Jamsek, Andrew K. Martin, Chandler McDowell, Robert K. Montoye, Hung C. Ngo, Jun Sawada

IBM J. Res. Dev., 2006

Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.

Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

Controlled-Load Limited Switch Dynamic Logic Circuit.

Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.

Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004

A low latency and low power dynamic Carry Save Adder.

Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.

Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns

IEEE J. Solid State Circuits, 2002

1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.

Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

IEEE J. Solid State Circuits, 1998

Design methodology for a 1.0 GHz microprocessor.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998