Hun-Hsien Chang

According to our database1, Hun-Hsien Chang authored at least 10 papers between 1995 and 2000.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2000
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits, 2000

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
ESD buses for whole-chip ESD protection.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
A 723-MHz 17.2-mW CMOS programmable counter.
IEEE J. Solid State Circuits, 1998

Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs.
IEEE J. Solid State Circuits, 1997

1996
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
IEEE Trans. Very Large Scale Integr. Syst., 1996

1995
A 550MHz 9.3mW CMOS Frequency Divider.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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