Huiyang Zhou
Orcid: 0000-0003-2133-0722
According to our database1,
Huiyang Zhou
authored at least 106 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Maximum Likelihood Quantum Error Mitigation for Algorithms with a Single Correct Output.
CoRR, 2024
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
QuTracer: Mitigating Quantum Gate and Measurement Errors by Tracing Subsets of Qubits.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
BoostCom: Towards Efficient Universal Fully Homomorphic Encryption by Boosting the Word-wise Comparisons.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024
2023
J. Parallel Distributed Comput., April, 2023
J. Grid Comput., March, 2023
Folding-Free ZNE: A Comprehensive Quantum Zero-Noise Extrapolation Approach for Mitigating Depolarizing and Decoherence Noise.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
IEEE Trans. Parallel Distributed Syst., 2022
CoRR, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent Memory.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata.
Proceedings of the ICS '21: 2021 International Conference on Supercomputing, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
2020
Fair and cache blocking aware warp scheduling for concurrent kernel execution on GPU.
Future Gener. Comput. Syst., 2020
CoRR, 2020
Proceedings of the Natural Language Processing and Chinese Computing, 2020
Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
MKPipe: a compiler framework for optimizing multi-kernel workloads in OpenCL for FPGA.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution.
ACM Trans. Archit. Code Optim., 2019
IEEE Comput. Archit. Lett., 2019
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Proceedings of the 12th Workshop on General Purpose Processing Using GPUs, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP.
ACM Trans. Archit. Code Optim., 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
POSTER: Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Enabling efficient preemption for SIMT architectures with lightweight context switching.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2015
J. Comput. Sci. Technol., 2015
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015
Proceedings of the 44th International Conference on Parallel Processing, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2014
Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Proceedings of the Numerical Computations with GPUs, 2014
2013
IEEE Trans. Computers, 2013
J. Parallel Distributed Comput., 2013
Int. J. Parallel Program., 2013
Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement.
Proceedings of the International Conference on Supercomputing, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Proceedings of the 41st International Conference on Parallel Processing, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
J. Instr. Level Parallelism, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
2010
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010
Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2010
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010
2009
Hardware-software integrated approaches to defend against software cache-based side channel attacks.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging.
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, 2009
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, 2009
2008
Address-branch correlation: A novel locality for long-latency hard-to-predict branches.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Deconstructing new cache designs for thwarting software cache-based side channel attacks.
Proceedings of the 2nd ACM Workshop on Computer Security Architecture, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
J. Instr. Level Parallelism, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
IEEE Trans. Computers, 2006
IEEE Comput. Archit. Lett., 2006
Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, 2006
2005
IEEE Trans. Computers, 2005
J. Instr. Level Parallelism, 2005
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005
2003
ACM Trans. Embed. Comput. Syst., 2003
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003
2002
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002
2001
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors.
Proceedings of the Languages and Compilers for Parallel Computing, 2001