Huimei Cheng

According to our database, Huimei Cheng authored at least 12 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.

Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020

SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol.

Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs.

Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.

Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics.

Huimei Cheng, Huan Huang, Kai Zhang

Math. Comput. Simul., 2019

Yield modelling and analysis of bundled data and ring-oscillator based designs.

Yang Zhang, Ji Li, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel

IET Comput. Digit. Tech., 2019

Automatic Conversion from Flip-flop to 3-phase Latch-based Designs.

Huimei Cheng, Yichen Gu, Peter A. Beerel

CoRR, 2019

2018

Area Optimization of Timing Resilient Designs Using Resynthesis.

Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.

Yang Zhang, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017

Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.

Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs.

Yang Zhang, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016

Area optimization of resilient designs guided by a mixed integer geometric program.

Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel

Proceedings of the 53rd Annual Design Automation Conference, 2016