Hui Wu

Orcid: 0009-0008-9150-5608

Affiliations:
  • University of Rochester, Rochester, NY, USA


According to our database1, Hui Wu authored at least 18 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Efficient LDPC Decoding using Physical Computation.
CoRR, 2023

Supporting Energy-based Learning with an Ising Machine substrate: a Case Study on RBM.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2019
Concurrent Multipoint-to-Multipoint Communication on Interposer Channels.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

To Stack or Not To Stack.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
An Energy-Efficient High-Swing PAM-4 Voltage-Mode Transmitter.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

High Swing Pulse-Amplitude Modulation of Transmission Line Links for On-Chip Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Design high bandwidth-density, low latency and energy efficient on-chip interconnect.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.
Microelectron. J., 2016

2015
A K-band pulse radar transceiver with highly digital closed-loop time-of-flight measurement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2012
Using Transmission Lines for Global On-Chip Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Enhancing effective throughput for transmission line-based bus.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
A design space exploration of transmission-line links for on-chip interconnect.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A case for globally shared-medium on-chip interconnect.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
An intra-chip free-space optical interconnect.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation.
IEEE J. Solid State Circuits, 2009

2008
Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2006
A reconfigurable, multi-gigahertz pulse shaping circuit based on distributed transversal filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Injection-Locked Clocking: A New GHz Clock Distribution Scheme.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


  Loading...