Hui Wang

Affiliations:
  • Chinese Academy of Sciences, Shanghai Advanced Research Institute, China
  • Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China (PhD 2001)


According to our database1, Hui Wang authored at least 28 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
BTPA: Hardware-Software Co-Design for Bitwise Based Transformer with Parallelized Accelerator.
Proceedings of the 10th IEEE International Conference on High Performance and Smart Computing, 2024

2023
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Multiscale deep network based multistep prediction of high-dimensional time series from power transmission systems.
Trans. Emerg. Telecommun. Technol., 2022

Transformer anomaly detection based on time-frequency domain software-hardware cooperative analysis.
Trans. Emerg. Telecommun. Technol., 2022

2021
An Efficient Small Traffic Sign Detection Method Based on YOLOv3.
J. Signal Process. Syst., 2021

An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 13-Bit, 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor.
Sensors, 2021

SparkNoC: An energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing.
J. Syst. Archit., 2021

A High-Efficiency Charge Pump for AMOLED Display Driver IC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 6-bit, 1GS/s Digital to Analog Converter for Automotive Ethernet PHY.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Anomaly Detection Based on RBM-LSTM Neural Network for CPS in Advanced Driver Assistance System.
ACM Trans. Cyber Phys. Syst., 2020

2019
Designing efficient accelerator of depthwise separable convolutional neural network on FPGA.
J. Syst. Archit., 2019

2018
A Novel Voltage-Programmed Pixel Circuit with Poly-Si TFTs for AMOLED Displays.
J. Circuits Syst. Comput., 2018

Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights.
Proceedings of the Smart Computing and Communication - Third International Conference, 2018

2017
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor.
IEEE Access, 2017

2015
A compact-sized 10-bit two-stage DAC for AMOLED column driver ICs.
IEICE Electron. Express, 2015

A novel current-biased voltage-programmed pixel circuit with low temperature polycrystalline silicon thin film transistors for AMOLED.
IEICE Electron. Express, 2015

A 21.4 pW/frame-pixel PWM image sensor with sub-threshold leakage reduction and two-step readout.
IEICE Electron. Express, 2015

CMOS image sensor with programmable compressed sensing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A quenching-and-reset circuit with programmable hold-off time for single photon avalanche diodes in 0.18μm CMOS.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

An area-efficient 10-bit two-stage DAC for active matrix organic light-emitting diodes display drivers.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Color image enhancement using power-constraint histogram equalization for AMOLED.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013
A low-power reconfigurable GFSK RF transceiver with sub-1GHz band for short range applications.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A power-constrained contrast enhancement algorithm for AMOLED display using histogram segmentation.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2010
Revealing Feasibility of FMM on ASIC: Efficient Implementation of N-Body Problem on FPGA.
Proceedings of the 13th IEEE International Conference on Computational Science and Engineering, 2010


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