Hui Wang

Orcid: 0000-0002-3394-1531

Affiliations:
  • Tsinghua University, Department of Electronic Engineering, TNList, Beijing, China


According to our database1, Hui Wang authored at least 37 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Designing scrubbing strategy for memories suffering MCUs through the selection of optimal interleaving distance.
Int. J. Comput. Sci. Eng., 2019

2014
A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A single channel, 6-bit 410-ms/s asynchronous SAR ADC based on 3bits/stage.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
Design Methodology of the Heterogeneous Multi-core Processor With the Combination of Parallelized Multi-core Simulator and Common Register File-Based Instruction Set Extension Architecture.
J. Comput., 2013

HS3DPG: Hierarchical simulation for 3D P/G network.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers.
IEICE Trans. Electron., 2011

Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding.
Proceedings of the 10th International Symposium on Autonomous Decentralized Systems, 2011

2010
Evaluation of Tunable Data Compression in Energy-Aware Wireless Sensor Networks.
Sensors, 2010

Output remapping technique for critical paths soft-error rate reduction.
IET Comput. Digit. Tech., 2010

Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting.
IET Circuits Devices Syst., 2010

Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks.
IEICE Trans. Commun., 2010

A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Energy efficient architecture of sensor network node based on compression accelerator.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.
Sci. China Ser. F Inf. Sci., 2008

Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Modified Conditional-Precharge Sense-amplifier-Based Flip-Flop with Improved Speed.
J. Circuits Syst. Comput., 2007

Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations.
Sci. China Ser. F Inf. Sci., 2007

Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Hybrid Genetic Algorithm with Critical Primary Inputs Sharing and Minor Primary Inputs Bits Climbing for Circuit Maximum Power Estimation.
Proceedings of the Third International Conference on Natural Computation, 2007

2006
Signal-Path-Level Dual-V<sub>T</sub> Assignment for Leakage Power Reduction.
J. Circuits Syst. Comput., 2006

A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Modeling the Impact of Process Variation on Critical Charge Distribution.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

IR-drop Reduction Through Combinational Circuit Partitioning.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Sigma-delta based clock recovery using on-chip PLL in FPGA.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Application of DAPSK in HF communications.
IEEE Commun. Lett., 2005

Improved Multiuser Detection for Fast FH/MFSK Systems.
Proceedings of the 2005 International Conference on Wireless Networks, 2005

A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

2002
An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits.
Sci. China Ser. F Inf. Sci., 2002

2001
Noise estimation for deep sub-micron integrated circuits.
Sci. China Ser. F Inf. Sci., 2001

1999
An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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