Hui Huang

Affiliations:
  • University of California, Los Angeles


According to our database1, Hui Huang authored at least 15 papers between 2000 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2016
A scalable communication-aware compilation flow for programmable accelerators.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
CMOST: a system-level FPGA compilation framework.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Compiler Support for Customizable Domain-Specific Computing.
PhD thesis, 2014

A Fully Pipelined and Dynamically Composable Architecture of CGRA.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Composable accelerator-rich microprocessor enhanced for adaptivity and longevity.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
Static and dynamic co-optimizations for blocks mapping in hybrid caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Compilation and architecture support for customized vector instruction extension.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Pattern-Mining for Behavioral Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

An energy-efficient adaptive hybrid cache.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A reuse-aware prefetching scheme for scratchpad memory.
Proceedings of the 48th Design Automation Conference, 2011

2010
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis.
Proceedings of the Design, Automation and Test in Europe, 2010

2005
Technology mapping and architecture evalution for <i>k/m</i>-macrocell-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2005

2000
Technology mapping for k/m-macrocell based FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Depth optimal incremental mapping for field programmable gate arrays.
Proceedings of the 37th Conference on Design Automation, 2000


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