Hui Guo

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

iCETD: An improved tag generation design for memory data authentication in embedded processor systems.

[BibT_eX]

[DOI]

Integr., 2017

Packet Leak Detection on Hardware-Trojan Infected NoCs for MPSoC Systems.

[BibT_eX]

[DOI]

Mubashir Hussain

Proceedings of the 2017 International Conference on Cryptography, Security and Privacy, 2017

2016

Fault-Tolerant Scheduling for Real-Time Scientific Workflows with Elastic Resource Provisioning in Virtualized Clouds.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

EONS: Minimizing Energy Consumption for Executing Real-Time Workflows in Virtualized Cloud Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

Data-Space Relocation to Improve Data Cache Performance for Embedded Multi-threaded Processor Systems.

[BibT_eX]

[DOI]

Mahanama Wickramasinghe

Proceedings of the Fifth International Conference on Network, Communication and Computing, 2016

Improving tag generation for memory data authentication in embedded processor systems.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Towards energy-efficient scheduling for real-time tasks under uncertain cloud computing environment.

[BibT_eX]

[DOI]

J. Syst. Softw., 2015

Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors.

[BibT_eX]

[DOI]

Mahanama Wickramasinghe

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and Implementation.

[BibT_eX]

[DOI]

Mahanama Wickramasinghe

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013

DLIC: Decoded loop instructions caching for energy-aware embedded processors.

[BibT_eX]

[DOI]

Tohru Ishihara

ACM Trans. Embed. Comput. Syst., 2013

Dynamic encryption key design and management for memory data encryption in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

Rolling-horizon scheduling for energy constrained distributed real-time embedded systems.

[BibT_eX]

[DOI]

J. Syst. Softw., 2012

A cost-effective tag design for memory data authentication in embedded systems.

[BibT_eX]

[DOI]

Xiaobo Sharon Hu

Proceedings of the 15th International Conference on Compilers, 2012

2011

An on-chip instruction cache design with one-bit tag for low-power embedded systems.

[BibT_eX]

[DOI]

Patrick Li

Microprocess. Microsystems, 2011

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems.

[BibT_eX]

[DOI]

Int. J. Handheld Comput. Res., 2011

2010

Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2010

An Energy Efficient Instruction Prefetching Scheme for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the Ubiquitous Computing and Multimedia Applications, 2010

FEDTIC: A Security Design for Embedded Systems with Insecure External Memory.

[BibT_eX]

[DOI]

Proceedings of the Future Generation Information Technology, 2010

Enabling large decoded instruction loop caching for energy-aware embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Compilers, 2010

2009

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

[BibT_eX]

[DOI]

Aleksandar Ignjatovic

IET Comput. Digit. Tech., 2009

An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2009

ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems.

[BibT_eX]

[DOI]

Patrick Li

Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Security Design for Multi-service Smart Card Systems.

[BibT_eX]

[DOI]

Bin Luo

Proceedings of the Second International Conference on Future Generation Communication and Networking, 2008

2006

Customization of application specific heterogeneous multi-pipeline processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Application specific forwarding network and instruction encoding for multi-pipe ASIPs.

[BibT_eX]

[DOI]

Aleksandar Ignjatovic

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Balancing System Level Pipelines with Stage Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004

Dual-pipeline heterogeneous ASIP design.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

1998

Power Reduction in Pipelines.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

Power consumption in CMOS combinational logic blocks at high frequencies.

[BibT_eX]

[DOI]