Hubert Kaeslin
Affiliations:- ETH Zurich, Switzerland
According to our database1,
Hubert Kaeslin
authored at least 52 papers
between 1986 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
IEEE Trans. Image Process., 2018
2016
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.
IEEE Trans. Circuits Syst. Video Technol., 2016
2015
Proceedings of the ICT Innovations for Sustainability, 2015
Proceedings of the 2015 Visual Communications and Image Processing, 2015
Proceedings of the 2015 Visual Communications and Image Processing, 2015
2014
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
2013
Evaluation and FPGA Implementation of Sparse Linear Solvers for Video Processing Applications.
IEEE Trans. Circuits Syst. Video Technol., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.
Proceedings of the ESSCIRC 2013, 2013
2012
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2012
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 20th European Signal Processing Conference, 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2008
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2008
Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
42% power savings through glitch-reducing clocking strategy in a hearing aid application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC.
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
A 0.67-mm<sup>2</sup> 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE Trans. Signal Process., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1997
IEEE J. Solid State Circuits, 1997
1996
Proceedings of the Parallel Problem Solving from Nature, 1996
1994
IEEE J. Solid State Circuits, March, 1994
1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1989
IEEE J. Solid State Circuits, August, 1989
1988
Behandlung der Umlaute bei der Verarbeitung deutscher Texte unter UNIX / How to Handle German Umlauts when Processing Documents under UNIX.
it Inf. Technol., 1988
Proceedings of the Graph-Theoretic Concepts in Computer Science, 1988
1986
IEEE Trans. Acoust. Speech Signal Process., 1986
A comparative study of the steady-state zones of German phones using centroids in the LPC parameter space.
Speech Commun., 1986