Hubert Harrer

According to our database1, Hubert Harrer authored at least 14 papers between 1992 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022

2015
Electronic packaging of the IBM z13 processor drawer.
IBM J. Res. Dev., 2015

2014
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits, 2014

2013

2012
Electronic packaging of the IBM System z196 enterprise-class server processor cage.
IBM J. Res. Dev., 2012

2009
Packaging design challenges of the IBM System z10 Enterprise Class server.
IBM J. Res. Dev., 2009

2007
High-speed interconnect and packaging design of the IBM System z9 processor cage.
IBM J. Res. Dev., 2007

2004
First- and second-level packaging of the z990 processor cage.
IBM J. Res. Dev., 2004

2002
First- and second-level packaging for the IBM eServer z900.
IBM J. Res. Dev., 2002

1994
A Current-Mode DTCNN Universal Chip .
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
On the convergence of discrete-time neural networks.
Int. J. Circuit Theory Appl., 1993

1992
Discrete time cellular neural networks.
PhD thesis, 1992

An analog implementation of discrete-time cellular neural networks.
IEEE Trans. Neural Networks, 1992

Discrete-time cellular neural networks.
Int. J. Circuit Theory Appl., 1992


  Loading...