Huawei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2024

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Soft Error Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Statistical Modeling of Soft Error Influence on Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., July, 2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

On-Line Fault Protection for ReRAM-Based Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning.

[BibT_eX]

[DOI]

J. Supercomput., 2023

Chosen ciphertext correlation power analysis on Kyber.

[BibT_eX]

[DOI]

Integr., 2023

SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks.

[BibT_eX]

[DOI]

CoRR, 2023

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library.

[BibT_eX]

[DOI]

CoRR, 2023

ChipGPT: How far are we from natural language hardware design.

[BibT_eX]

[DOI]

CoRR, 2023

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Reliability Analysis of Vision Transformers.

[BibT_eX]

[DOI]

CoRR, 2023

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

Fast Exact NPN Classification with Influence-Aided Canonical Form.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

APPEND: Rethinking ASIP Synthesis in the Era of AI.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A Template Attack on Reduction Without Reference Device on Kyber.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Message from the Chairs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Taming Process Variations in CNFET for Efficient Last-Level Cache Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Fast Precision Tuning Solution for Always-On DNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

CoRR, 2022

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2022

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

SASH: Efficient secure aggregation based on SHPRG for federated learning.

[BibT_eX]

[DOI]

Proceedings of the Uncertainty in Artificial Intelligence, 2022

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

VStore: in-storage graph based vector search accelerator.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Hardware Trojan Trigger Localization Method in RTL based on Control Flow Features.

[BibT_eX]

[DOI]

Proceedings of the IEEE 31st Asian Test Symposium, 2022

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

An Edge 3D CNN Accelerator for Low-Power Activity Recognition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Efficient Secure Aggregation Based on SHPRG For Federated Learning.

[BibT_eX]

[DOI]

CoRR, 2021

Taming Process Variations in CNFET for Efficient Last Level Cache Design.

[BibT_eX]

[DOI]

CoRR, 2021

Energy-Efficient Accelerator Design for Deformable Convolution Networks.

[BibT_eX]

[DOI]

CoRR, 2021

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2021

Editorial for the special issue on reliability and power efficiency for HPC.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2021

Special Session - Test for AI Chips: from DFT to On-line Testing.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

GLIST: Towards In-Storage Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 2021 USENIX Annual Technical Conference, 2021

Scalable Parallel Static Learning.

[BibT_eX]

[DOI]

Xiaoze Lin

Liyang Lai

Proceedings of the IEEE International Test Conference in Asia, 2021

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

GCiM: A Near-Data Processing Accelerator for Graph Construction.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SeGa: A Trojan Detection Method Combined With Gate Semantics.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Architecting Effectual Computation for Machine Learning Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

GPGPU-Based ATPG System: Myth or Reality?

[BibT_eX]

[DOI]

Liyang Lai

Kun-Han Tsai

Sarath Mohanachandran Nair

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Evaluating and Constraining Hardware Assertions with Absent Scenarios.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2020

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.

[BibT_eX]

[DOI]

IEEE Access, 2020

A New Secure Scan Design with PUF-based Key for Authentication.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Sequence Triggered Hardware Trojan in Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Said Hamdioui

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

HIT: A Hidden Instruction Trojan Model for Processors.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

An Efficient Deep Learning Accelerator for Compressed Video Analysis.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Towards State-Aware Computation in ReRAM Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Survey: Hardware Trojan Detection for Netlist.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A QoS-QoR Aware CNN Accelerator Design Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection.

[BibT_eX]

[DOI]

CoRR, 2019

Scan Chain Based Attacks and Countermeasures: A Survey.

[BibT_eX]

[DOI]

IEEE Access, 2019

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Secure and Low-overhead Active IC Metering Scheme.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2019 USENIX Annual Technical Conference, 2019

A Memristor-based Scan Hold Flip-Flop.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Non-Volatile Memory Systems and Applications Symposium, 2019

China Test Conference (CTC) - Extending the Global Test Forum to China.

[BibT_eX]

[DOI]

Yinhe Han

Proceedings of the IEEE International Test Conference, 2019

Implementation of Parametric Hardware Trojan in FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Squeezing the Last MHz for CNN Acceleration on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Instruction Vulnerability Test and Code Optimization Against DVFS Attack.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Fuzzy Association Rule Mining Algorithm Based on Load Classifier.

[BibT_eX]

[DOI]

Proceedings of the Data Science - 6th International Conference, 2019

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

An Agile Precision-Tunable CNN Accelerator based on ReRAM.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

GramsDet: Hardware Trojan Detection Based on Recurrent Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Exploring emerging CNFET for efficient last level cache design.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

P<sup>3</sup>M: a PIM-based neural network model protection scheme for deep learning accelerator.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Neural Network Training for Accelerators with Computing Errors.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Innovative practices on challenges, opportunities, and solutions to hardware security.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Lightweight Timing Channel Protection for Shared DRAM Controller.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Small Trojan Testing Using Bounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

FCN-engine: accelerating deconvolutional layers in classic CNN processors.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A retrospective evaluation of energy-efficient object detection solutions on embedded devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Hardware Trojan Detection Based on Signal Correlation.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A New Scheme to Extract PUF Information by Scan Chain.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

XORiM: A case of in-memory bit-comparator implementation and its performance implications.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A low-overhead PUF based on parallel scan design.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Bias PUF based Secure Scan Chain Design.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Retention-Aware DRAM Assembly and Repair for Future FGR Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Why current secure scan designs fail and how to fix them?

[BibT_eX]

[DOI]

Integr., 2017

Innovative practices session 10C formal verification practices in industry.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Flip-flop clustering based trace signal selection for post-silicon debug.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Software-based online self-testing of network-on-chip using bounded model checking.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Jianhui Jiang

Proceedings of the IEEE International Test Conference, 2017

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

How to Secure Scan Design Against Scan-Based Side-Channel Attacks?

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

A New Active IC Metering Technique Based on Locking Scan Cells.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

On Evaluating and Constraining Assertions Using Conflicts in Absent Scenarios.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Abstraction-Guided Simulation Using Markov Analysis for Functional Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs.

[BibT_eX]

[DOI]

Integr., 2016

Path constraint solving based test generation for observability-enhanced branch coverage.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

An accurate algorithm for computing mutation coverage in model checking.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

A new countermeasure against scan-based side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

An ultra-low overhead LUT-based PUF for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA Tools.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Data Remapping for Static NUCA in Degradable Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Economizing TSV Resources in 3-D Network-on-Chip Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An on-chip frequency programmable test clock generation and application method for small delay defect detection.

[BibT_eX]

[DOI]

Integr., 2015

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A case of precision-tunable STT-RAM memory design for approximate neural network.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Temperature-aware software-based self-testing for delay faults.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Retraining-based timing error mitigation for hardware neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

<i>RADAR</i>: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

TURO: A lightweight turn-guided routing scheme for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Lightweight Timing Channel Protection for Shared Memory Controllers.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2014

Reinventing Memory System Design for Many-Accelerator Architecture.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2014

A novel abstraction-guided simulation approach using posterior probabilities for verification.

[BibT_eX]

[DOI]

Jian Wang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Functional test generation guided by steady-state probabilities of abstract design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A low power DRAM refresh control scheme for 3D memory cube.

[BibT_eX]

[DOI]

Yinhe Han

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

An On-Line Timing Error Detection Method for Silicon Debug.

[BibT_eX]

[DOI]

Yun Cheng

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Test Path Selection for Capturing Delay Failures Under Statistical Timing Model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

RSAK: Random stream attack for phase change memory in video applications.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Path Constraint Solving Based Test Generation for Hard-to-Reach States.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A High-Precision On-Chip Path Delay Measurement Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Testable Path Selection and Grouping for Faster Than At-Speed Testing.

[BibT_eX]

[DOI]

Xiang Fu

IEEE Trans. Very Large Scale Integr. Syst., 2012

Statistical SDFC: A metric for evaluating test quality of small delay faults.

[BibT_eX]

[DOI]

Xuefeng Zhu

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Path Delay Test Generation Toward Activation of Worst Case Coupling Effects.

[BibT_eX]

[DOI]

Minjin Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2011

Statistical lifetime reliability optimization considering joint effect of process variation and aging.

[BibT_eX]

[DOI]

Integr., 2011

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

A unified test architecture for on-line and off-line delay fault detections.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

An abacus turn model for time/space-efficient reconfigurable routing.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Flex memory: Exploiting and managing abundant off-chip optical bandwidth.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Testable Critical Path Selection Considering Process Variation.

[BibT_eX]

[DOI]

Xiang Fu

IEICE Trans. Inf. Syst., 2010

Fast path selection for testing of small delay defects considering path correlations.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

On generation of a universal path candidate set containing testable long paths.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

An on-chip clock generation scheme for faster-than-at-speed delay testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Software-Based Self-Testing of Processors Using Expanded Instructions.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing.

[BibT_eX]

[DOI]

Xiang Fu

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Graph partition based path selection for testing of small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2009

Automatic Selection of Internal Observation Signals for Design Verification.

[BibT_eX]

[DOI]

Tao Lv

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Impact of Hazards on Pattern Selection for Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Small Delay Fault Simulation for Sequential Circuits.

[BibT_eX]

[DOI]

Li Liu

Jishun Kuang

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Low Overhead On-Chip Path Delay Measurement Circuit.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Multiple Coupling Effects Oriented Path Delay Test Generation.

[BibT_eX]

[DOI]

Minjin Zhang

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Static Crosstalk Noise Analysis with Transition Map.

[BibT_eX]

[DOI]

Minjin Zhang

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Case Study on At-Speed Testing for a Gigahertz Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Scan-Based Delay Test Method for Reduction of Overtesting.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robust test generation for power supply noise induced path delay faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

The design-for-testability features of a general purpose microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Bug analysis and corresponding error models in real designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Routing Algorithm for Random Error Tolerance in Network-on-Chip.

[BibT_eX]

[DOI]

Lei Zhang

Proceedings of the Human-Computer Interaction. HCI Applications and Services, 2007

2006

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

Response compaction for system-on-a-chip based on advanced convolutional codes.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2006

Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.

[BibT_eX]

[DOI]

Pei-Fu Shen

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fast Packet Classification using Group Bit Vector.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define Chains.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

An innovative free memory design for network processors in home network gateway.

[BibT_eX]

[DOI]

Shuguang Gong

IEEE Trans. Consumer Electron., 2005

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Selection of Crosstalk-Induced Faults in Enhanced Delay Test.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Using MUXs Network to Hide Bunches of Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Non-robust Test Generation for Crosstalk-Induced Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design of an efficient memory subsystem for network processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Pair Balance-Based Test Scheduling for SOCs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Rapid and Energy-Efficient Testing for Embedded Cores.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

A Novel RT-Level Behavioral Description Based ATPG Method.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2003

Delay Test Pattern Generation Considering Crosstalk-Induced Effects.

[BibT_eX]

[DOI]

Yue Zhang

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Clustering of behavioral phases in FSMs and its applications to VLSI test.

[BibT_eX]

[DOI]

Sci. China Ser. F Inf. Sci., 2002

Test Power Optimization Techniques for CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Reducing Power Dissipation during At-Speed Test Application.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

An RT-Level ATPG Based on Clustering of Circuit States.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Reduction of Number of Paths to be Tested in Delay Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

1998

Delay Testing with Double Observations.

[BibT_eX]

[DOI]