Huang-Lun Lin

According to our database, Huang-Lun Lin authored at least 5 papers between 2011 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Low power 3-D stacking multimedia platform with reconfigurable memory architecture.

Po-Han Huang, Huang-Lun Lin, Hsien-Ching Hsieh, Chi-Hung Lin, Shui-An Wen, Yi-Fa Sun

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC.

Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin

Proceedings of the IEEE 25th International SOC Conference, 2012

Low power and high performance 3-D multimedia platform.

Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011

Power-aware design technique for PAC Duo based embedded system.

Shui-An Wen, Huang-Lun Lin, Chi Wu, Chun-Chin Chen, Kun-Hsien Tsai, Wei-Min Cheng

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Low power design and dynamic power management system for VLIW DSP subsystem.

Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011