Huan-Chih Tsai

According to our database, Huan-Chih Tsai authored at least 7 papers between 1997 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

On improving test quality of scan-based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Static property checking using ATPG vs. BDD techniques.

Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A testability metric for path delay faults and its application.

Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal

Proceedings of ASP-DAC 2000, 2000

1999

Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme.

Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik

Proceedings of the 36th Conference on Design Automation, 1999

1998

Efficient test-point selection for scan-based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik

IEEE Trans. Very Large Scale Integr. Syst., 1998

An almost full-scan BIST solution-higher fault coverage and shorter test application time.

Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

A Hybrid Algorithm for Test Point Selection for Scan-Based BIST.

Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik

Proceedings of the 34st Conference on Design Automation, 1997