Huaguo Liang

Frontiers Inf. Technol. Electron. Eng., October, 2024

Voltage Skew-Based Test Technique for Pre-Bond TSVs in 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

NEST: A Quadruple-Node Upset Recovery Latch Design and Algorithm-Based Recovery Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., August, 2024

DBU-PG: energy-efficient noc design using dual-buffering power gating.

[BibT_eX]

[DOI]

J. Supercomput., July, 2024

Lightweight Hybrid Entropy Source True Random Number Generator Based on Jitter and Metastability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision.

[BibT_eX]

[DOI]

J. Electron. Test., June, 2024

A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., March, 2024

Reliability analysis and comparison of ring-PUF based on probabilistic models.

[BibT_eX]

[DOI]

Microelectron. J., February, 2024

A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches.

[BibT_eX]

[DOI]

J. Electron. Test., February, 2024

A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements.

[BibT_eX]

[DOI]

J. Electron. Test., February, 2024

A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., January, 2024

Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A Symmetric Bridge-Based Pre-Bond TSV Faults Detection Method.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

A Scan-Chain-Based Built-in Self-Test for ILV in Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Fault-tolerant routing for reliable packet transmission in on-chip networks.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator.

[BibT_eX]

[DOI]

Microelectron. J., 2024

SPONGE+: A NoC-based power gating scheme for overall router column opening and closing control.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A lightweight reversible multi-mode physical unclonable function.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process.

[BibT_eX]

[DOI]

Microelectron. J., 2024

High throughput dynamic dual entropy source true random number generator based on FPGA.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A Low-Cost Triple-Node-Upset Self-Recovery Latch Design.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2024

Design of novel low cost triple-node-upset self-recoverable hardened latch.

[BibT_eX]

[DOI]

Integr., 2024

A self-training end-to-end mask optimization framework based on semantic segmentation network.

[BibT_eX]

[DOI]

Integr., 2024

Multi-transition delay test for improving the coverage of cell internal defects.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

A machine learning resistant PUF circuit adjustment method based on strict avalanche criterion.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

PFO PUF: A Lightweight Parallel Feed Obfuscation PUF Resistant to Machine Learning Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

A RO-Integrated-LFSR-Based Nonlinear Strong PUF with Intrinsic Modeling Attacks Resilience.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

2023

RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.

[BibT_eX]

[DOI]

IEEE Trans. Aerosp. Electron. Syst., December, 2023

Improving power and performance of on-chip network through virtual channel sharing and power gating.

[BibT_eX]

[DOI]

Integr., November, 2023

Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling.

[BibT_eX]

[DOI]

Liang Yao

Yingchun Lu

J. Supercomput., October, 2023

URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators.

[BibT_eX]

[DOI]

J. Supercomput., September, 2023

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., August, 2023

Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets.

[BibT_eX]

[DOI]

J. Electron. Test., June, 2023

Design of approximate Booth multipliers based on error compensation.

[BibT_eX]

[DOI]

Integr., May, 2023

Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC.

[BibT_eX]

[DOI]

Integr., May, 2023

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator.

[BibT_eX]

[DOI]

Microelectron. J., March, 2023

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.

[BibT_eX]

[DOI]

Microelectron. J., 2023

Fault-avoidance C-element based low overhead and TNU-resilient latch.

[BibT_eX]

[DOI]

Microelectron. J., 2023

LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy.

[BibT_eX]

[DOI]

Integr., 2023

2022

A router architecture with dual input and dual output channels for Networks-on-Chip.

[BibT_eX]

[DOI]

Microprocess. Microsystems, April, 2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A reconfigurable PUF structure with dual working modes based on entropy separation model.

[BibT_eX]

[DOI]

Microelectron. J., 2022

REE: Reconfigurable and energy-efficient router architecture in wireless network-on-chip.

[BibT_eX]

[DOI]

Microelectron. J., 2022

Design of fully adaptive routing and hybrid VC allocation in wireless NOC.

[BibT_eX]

[DOI]

Microelectron. J., 2022

Architecting a congestion pre-avoidance and load-balanced wireless network-on-chip.

[BibT_eX]

[DOI]

Chenglong Sun

Yiming Ouyang

J. Parallel Distributed Comput., 2022

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2022

A reconfigurable test method based on LFSR for 3D stacking integrated circuits.

[BibT_eX]

[DOI]

Integr., 2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2022

A Lightweight M_TRNG Design based on MUX Cell Entropy using Multiphase Sampling.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A high reliability physically unclonable function based on multiple tunable ring oscillator.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A high-speed and triple-node-upset recovery latch with heterogeneous interconnection.

[BibT_eX]

[DOI]

Microelectron. J., 2021

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Design of MNU-Resilient latches based on input-split C-elements.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Design of node separated triple-node-upset self-recoverable latch.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.

[BibT_eX]

[DOI]

Integr., 2021

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch.

[BibT_eX]

[DOI]

IEEE Access, 2021

A N: 1 Single-Channel TDMA Fault-Tolerant Technique for TSVs in 3D-ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Architecture of Cobweb-Based Redundant TSV for Clustered Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

cm<sup>3</sup>WiNoCs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Access, 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.

[BibT_eX]

[DOI]

IEEE Access, 2020

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC.

[BibT_eX]

[DOI]

IEEE Access, 2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.

[BibT_eX]

[DOI]

IEEE Access, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Multi-task Scheduling for PIM-based Heterogeneous Computing System.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Design of Wireless Network on Chip with Priority-Based MAC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness.

[BibT_eX]

[DOI]

Integr., 2019

DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Temperature-Aware Floorplanning for Fixed-Outline 3D ICs.

[BibT_eX]

[DOI]

IEEE Access, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

2018

Design of Low-Power WiNoC with Congestion-Aware Wireless Node.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

An improved communication scheme for non-HOL-blocking wireless NoC.

[BibT_eX]

[DOI]

Integr., 2018

MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A High Reliability FPGA Chip Identification Generator Based on PDLs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Dictionary-Based Test Data Compression Method Using Tri-State Coding.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2017

A transient pulse dually filterable and online self-recoverable latch.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2016

Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

NBTI mitigation by M-IVC with input duty cycle and randomness constraints.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2015

A High Performance SEU Tolerant Latch.

[BibT_eX]

[DOI]

J. Electron. Test., 2015

Pulse shrinkage based pre-bond through silicon vias test in 3D IC.

[BibT_eX]

[DOI]

Chang Hao

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

NBTI-induced circuit aging optimization by protectability-aware gate replacement technique.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

MTTF-Aware Reliability Task Scheduling for Heterogeneous Multicore System.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014

Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Design of a Radiation Hardened Latch for Low-Power Circuits.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A dynamic self-adaptive correction method for error resilient application.

[BibT_eX]

[DOI]

Luming Yan

Proceedings of the Design, Automation and Test in Europe, 2013

2010

A Novel x -ploiting Strategy for Improving Performance of Test Data Compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A scheme of test data compression based on coding of even bits marking and selective output inversion.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2010

2009

Impact of Hazards on Pattern Selection for Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding.

[BibT_eX]

[DOI]

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008

Balancing wrapper chains of SoC core based on best interchange decreasing.

[BibT_eX]

[DOI]

Maoxiang Yi

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007

Test data compression scheme based on variable-to-fixed-plus-variable-length coding.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

A Novel Collaborative Scheme of Test Data Compression Based on Fixed-Plus-variable-Length Coding.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Block Marking and Updating Coding in Test Data Compression for SoC.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2005

A BIST Scheme Based on Selecting State Generation of Folding Counters.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

A new technique for deterministic scan based built in self test (BIST).

[BibT_eX]

[DOI]

PhD thesis, 2003

Sharing BIST with Multiple Cores for System-on-a-Chip.

[BibT_eX]

[DOI]

Cuiyun Jiang

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

A Mixed-Mode BIST Scheme Based on Folding Compression.

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

J. Electron. Test., 2002

2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.

[BibT_eX]

[DOI]