Hu He

According to our database, Hu He authored at least 33 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Ventus: A High-performance Open-source GPGPU Based on RISC-V and Its Vector Extension.

Jingzhou Li, Kexiang Yang, Chufeng Jin, Xudong Liu, Zexia Yang, Fangfei Yu, Yujie Shi, Mingyuan Ma, Li Kong, Jing Zhou, Hualin Wu, Hu He

Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors.

Jingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.

Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system.

Ruihua Yu, Wenqiang Zhang, Bin Gao, Yiwen Geng, Peng Yao, Yuyi Liu, Qingtian Zhang, Jianshi Tang, Dong Wu, Hu He, Ning Deng, He Qian, Huaqiang Wu

Sci. China Inf. Sci., December, 2023

A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit.

Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Jian Yu, Dabin Wu, Junren Chen, Qingtian Zhang, Xing Mou, He Qian, Huaqiang Wu

IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing.

Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Qingtian Zhang, He Qian, Huaqiang Wu

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2021

A memory neural system built based on spiking neural network.

Hu He, Qilin Wang, Xu Yang, Yunlin Lei, Jia Cai, Ning Deng

Neurocomputing, 2021

HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU.

Yanhai Jiang, Bin Gao, Jianshi Tang, Dabin Wu, Hu He, He Qian, Huaqiang Wu

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020

The Algorithm of Spiking Neural Network And Application in Poker Games.

Liya Dong, Qilin Wang, Hu He

Proceedings of the ICMSSP 2020: 5th International Conference on Multimedia Systems and Signal Processing, 2020

2019

On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness.

Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things.

Xu Yang, Yumin Hou, Junping Ma, Hu He

Sensors, 2019

A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications.

Xu Yang, Yumin Hou, Hu He

Sensors, 2019

Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods.

Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He, Xu Yang

J. Circuits Syst. Comput., 2019

Exploration of a mechanism to form bionic, self-growing and self-organizing neural network.

Xu Yang, Guo Liu, Songgaojun Deng, Zichao Wei, Hu He, Yingjie Shang, Ning Deng

Artif. Intell. Rev., 2019

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.

Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

R2D2: Runtime reassurance and detection of A2 Trojan.

Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017

On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage.

Hu He, Xu Yang, Yanjun Zhang

Comput. J., 2017

2016

FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.

Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu

VLSI Design, 2016

2014

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.

Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He

IEEE Trans. Very Large Scale Integr. Syst., 2014

An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems.

Xu Yang, Deyuan Guo, Hu He, Haijing Tang, Yanjun Zhang

Comput. J., 2014

2013

Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems.

Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He

IET Wirel. Sens. Syst., 2013

2012

An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems.

Xu Yang, Hu He

Sensors, 2012

2011

Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.

Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan

J. Electron. Test., 2011

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.

Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan

J. Electron. Test., 2011

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).

Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2009

A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures.

Yang Xu, Hu He, Yihe Sun

J. Low Power Electron., 2009

Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism.

Zheng Shen, Hu He, Yihe Sun

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.

Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

A Video Specific Instruction Set Architecture for ASIP design.

Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun

VLSI Design, 2007

Heuristic on a Novel Power Management System Cooperating with Compiler.

Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun

J. Low Power Electron., 2007

A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture.

Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.

Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun

Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006

2005

A new register file access architecture for software pipelining in VLIW processors.

Yanjun Zhang, Hu He, Yihe Sun

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005