Hsuan-Yu Chiang

According to our database, Hsuan-Yu Chiang authored at least 1 paper in 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Systolic Array-Based Accelerator Architecture Combining Iterative Variable-Width Approximate Multipliers.

Po-Ying Feng, Shih-Nung Lee, Yong-Chi Chang, Hsuan-Yu Chiang, Shu-Yen Lin

Proceedings of the 13th IEEE Global Conference on Consumer Electronics, 2024