Hsuan-Jung Hsu

According to our database, Hsuan-Jung Hsu authored at least 6 papers between 2007 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

AC-Plus Scan Methodology for Small Delay Testing and Characterization.

Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2013

2011

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme.

Hsuan-Jung Hsu, Shi-Yu Huang

IEEE Trans. Very Large Scale Integr. Syst., 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.

Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang

Proceedings of the 48th Design Automation Conference, 2011

2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.

Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Resilient Self-V_DD-Tuning Scheme With Speed-Margining for Low-Power SRAM.

Ya-Chun Lai, Shi-Yu Huang, Hsuan-Jung Hsu

IEEE J. Solid State Circuits, 2009

2007

Built-In Speed Grading with a Process-Tolerant ADPLL.

Hsuan-Jung Hsu, Chun-Chieh Tu, Shi-Yu Huang

Proceedings of the 16th Asian Test Symposium, 2007