Hsu-Kang Dow

Orcid: 0000-0001-6062-9255

According to our database1, Hsu-Kang Dow authored at least 5 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2022
HWST128: complete memory safety accelerator on RISC-V with metadata compression.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2019
A Bio-Sensing System-on-Chip and Software for Smart Clothes.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2018
A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2015
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.
Proceedings of the VLSI Design, Automation and Test, 2015


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