Hsiu-Ming Chang

Affiliations:
  • Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, USA


According to our database1, Hsiu-Ming Chang authored at least 20 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to power system modeling and analysis tools for protective relaying".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing.
J. Electron. Test., 2012

2011
Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Time-Multiplexed Online Checking.
IEEE Trans. Computers, 2011

Test cost reduction through performance prediction using virtual probe.
Proceedings of the 2011 IEEE International Test Conference, 2011

An all-digital built-in self-test technique for transfer function characterization of RF PLLs.
Proceedings of the Design, Automation and Test in Europe, 2011

Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers.
Proceedings of the 48th Design Automation Conference, 2011

A self-testing and calibration method for embedded successive approximation register ADC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Recent Advances in Analog, Mixed-Signal, and RF Testing.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study.
J. Electron. Test., 2010

Calibration-assisted production testing for digitally-calibrated ADCs.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

An error tolerance scheme for 3D CMOS imagers.
Proceedings of the 47th Design Automation Conference, 2010

2009
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.
IEEE J. Solid State Circuits, 2009

Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

A Built-in self-calibration scheme for pipelined ADCs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Test strategies for adaptive equalizers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Calibration as a Functional Test: An ADC Case Study.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A charge pump-based direct frequency modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Time-Multiplexed Online Checking: A Feasibility Study.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs.
Proceedings of the 17th IEEE Asian Test Symposium, 2008


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