Hsiu-Chuan Shih

According to our database, Hsiu-Chuan Shih authored at least 6 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.

Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu

IEEE Des. Test, 2017

2015

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.

Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu

Proceedings of the Symposium on VLSI Circuits, 2015

2014

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.

Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

An enhanced double-TSV scheme for defect tolerance in 3D-IC.

Hsiu-Chuan Shih, Cheng-Wen Wu

Proceedings of the Design, Automation and Test in Europe, 2013

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.

Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011

Training-based forming process for RRAM yield improvement.

Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu

Proceedings of the 29th IEEE VLSI Test Symposium, 2011