Hsin-Po Wang

According to our database, Hsin-Po Wang authored at least 4 papers between 2000 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Type-matching clock tree for zero skew clock gating.

Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu

Proceedings of the 45th Design Automation Conference, 2008

2001

A Flexible Logic BIST Scheme and Its Application to SoC Designs.

Xiaoqing Wen, Hsin-Po Wang

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.

Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

DFT and BIST techniques for the future.

Hsin-Po Wang, Jon Turino

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000