Hsien-Yuan Liao
According to our database1,
Hsien-Yuan Liao
authored at least 5 papers
between 2008 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
2008
2010
2012
2014
2016
2018
2020
0
1
2
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2014
Proceedings of the Symposium on VLSI Circuits, 2014
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
Design formula for band-switching capacitor array in wide tuning range low-phase-noise LC-VCO.
Microelectron. J., 2008