Hsien-Ching Hsieh

According to our database, Hsien-Ching Hsieh authored at least 9 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system.

Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang

Proceedings of the IEEE International Conference on Acoustics, 2014

2013

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform.

Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Low power 3-D stacking multimedia platform with reconfigurable memory architecture.

Po-Han Huang, Huang-Lun Lin, Hsien-Ching Hsieh, Chi-Hung Lin, Shui-An Wen, Yi-Fa Sun

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC.

Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin

Proceedings of the IEEE 25th International SOC Conference, 2012

High resolution and frame rate image signal processor array design for 3-D imager.

Chang-Hsin Cheng, Hsien-Ching Hsieh, Tso-Yi Fan, Wei-Xiang Tang, Chung-Kai Liu, Po-Han Huang

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.

Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Low power and high performance 3-D multimedia platform.

Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011

Low power design and dynamic power management system for VLIW DSP subsystem.

Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

System-level design exploration for 3-D stacked memory architectures.

Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011