Hsie-Chia Chang

IEEE Open J. Circuits Syst., 2022

A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND.

[BibT_eX]

[DOI]

Li-Wei Liu

Proceedings of the IEEE International Conference on Acoustics, 2022

An Attention-based Neural Network on Multiple Speaker Diarization.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

A Two-Stage Path Planning Engine for Robot Navigation System.

[BibT_eX]

[DOI]

Yu-En Hsu

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 45.4x∼221.2x latency Improvement of SRP-5 Cryptographic Engine for Smart Grid Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications.

[BibT_eX]

[DOI]

Wei Chiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Generalized Globally-Coupled Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

Shu Lin

Proceedings of the IEEE Information Theory Workshop, 2018

Scalable Globally-Coupled Low-Density Parity Check Codes.

[BibT_eX]

[DOI]

Shu Lin

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A 188-Length Full Code Rate 333Mbps 1.08mm2 Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Re-Polarization Processing in Extended Polar Codes.

[BibT_eX]

[DOI]

Yu-Ming Huang

Hsiang-Pang Li

IEICE Trans. Commun., 2017

2016

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.

[BibT_eX]

[DOI]

Kin-Chu Ho

Chih-Lung Chen

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder.

[BibT_eX]

[DOI]

Chen-Yang Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design of LT code degree distribution with profiled output ripple size.

[BibT_eX]

[DOI]

Kuo-Kuang Yen

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2014

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.

[BibT_eX]

[DOI]

Yi-Min Lin

IEEE Trans. Very Large Scale Integr. Syst., 2013

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2013

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis.

[BibT_eX]

[DOI]

Chen-Yang Lin

IEEE J. Solid State Circuits, 2013

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2013

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.

[BibT_eX]

[DOI]

Chih-Lung Chen

IEEE Commun. Lett., 2013

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Wireless Communications and Signal Processing, 2013

Processor with side-channel attack resistance.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine.

[BibT_eX]

[DOI]

Kin-Chu Ho

Po-Chao Fang

Hsiang-Pang Li

Cheng-Yuan Michael Wang

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An area-efficient BCH codec with echelon scheduling for NAND flash applications.

[BibT_eX]

[DOI]

Chi-Heng Yang

Yi-Hsun Chen

Proceedings of IEEE International Conference on Communications, 2013

2012

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine.

[BibT_eX]

[DOI]

Po-Chun Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2012

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A low cost DPA-resistant 8-bit AES core based on ring oscillators.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories.

[BibT_eX]

[DOI]

Yi-Hsun Chen

Chi-Heng Yang

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An improved LT encoding scheme with extended chain lengths.

[BibT_eX]

[DOI]

Kuo-Kuang Yen

Chih-Lung Chen

Proceedings of the International Symposium on Information Theory and its Applications, 2012

Stochastic decoding for LDPC convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A fully parallel BCH codec with double error correcting capability for NOR flash applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.

[BibT_eX]

[DOI]

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators.

[BibT_eX]

[DOI]

Po-Chun Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

A multiple code-rate turbo decoder based on reciprocal dual trellis architecture.

[BibT_eX]

[DOI]

Chen-Yang Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An improved soft BCH decoder with one extra error compensation.

[BibT_eX]

[DOI]

Yi-Min Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance.

[BibT_eX]

[DOI]

Proceedings of the 36th European Solid-State Circuits Conference, 2010

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.

[BibT_eX]

[DOI]

Xin-Ru Lee

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit.

[BibT_eX]

[DOI]

Po-Chun Liu

Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 11.5-Gbps LDPC decoder based on CP-PEG code construction.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Multi-mode message passing switch networks applied for QC-LDPC decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Structured LDPCcodes with low error floor based on PEG tanner graphs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints.

[BibT_eX]

[DOI]

Proceedings of IEEE International Conference on Communications, 2008

2007

Self-Compensation Technique for Simplified Belief-Propagation Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2007

Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A low power turbo/Viterbi decoder for 3GPP2 applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Carry Estimation for Two's Complement Fixed-Width Multipliers.

[BibT_eX]

[DOI]

Chih-Wei Liu

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A self-compensation fixed-width booth multiplier and its 128-point FFT applications.

[BibT_eX]

[DOI]

Hong-An Huang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Design of a power-reduction Viterbi decoder for WLAN applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A 3.33Gb/s (1200,720) low-density parity check code decoder.

[BibT_eX]

[DOI]

Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004

A power and area efficient multi-mode FEC processor.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Multi-level memory systems using error control codes.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A dual mode channel decoder for 3GPP2 mobile wireless communications.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

A Low-Power Design for Reed-Solomon Decoders.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2003

2001

A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications.

[BibT_eX]

[DOI]

C. Bernard Shung

IEEE J. Solid State Circuits, 2001

An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999

New serial architecture for the Berlekamp-Massey algorithm.

[BibT_eX]

[DOI]

C. Bernard Shung

IEEE Trans. Commun., 1999

1998

A (208, 192;8) Reed-Solomon decoder for DVD application.

[BibT_eX]

[DOI]