Hsiao-Ping Juan

According to our database1, Hsiao-Ping Juan authored at least 5 papers between 1993 and 1996.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
Clock-driven performance optimization in interactive behavioral synthesis.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Clock optimization for high-performance pipelined design.
Proceedings of the conference on European design automation, 1996

Component selection in resource shared and pipelined DSP applications.
Proceedings of the conference on European design automation, 1996

1994
Condition graphs for high-quality behavioral synthesis.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Top-down modeling of RISC processors in VHDL.
Proceedings of the European Design Automation Conference 1993, 1993


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