Hsiang-Yun Wei

According to our database1, Hsiang-Yun Wei authored at least 1 paper in 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A low jitter delay-locked-loop applied for DDR4.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013


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