Hsiang-Yun Cheng

According to our database, Hsiang-Yun Cheng authored at least 31 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning.

Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Wu

CoRR, 2024

ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems.

Hao-Wei Chiang, Chin-Fu Nien, Hsiang-Yun Cheng, Kuei-Po Huang

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis.

Tsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network.

Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Tensor Movement Orchestration in Multi-GPU Training Systems.

Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications.

Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng

Proceedings of the International Conference on Compilers, 2023

2022

DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.

Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien

ACM Trans. Embed. Comput. Syst., 2022

Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.

Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li

Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022

Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement.

He-Sheng Chou, Hsiang-Yun Cheng, Jun-Xiang Qiu, Tsun-Kuang Chi, Tsung-Yi Chen, Shin-Lun Chen

Proceedings of the IEEE International Conference on Consumer Electronics, 2022

Efficient Bad Block Management with Cluster Similarity.

Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment.

Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator.

Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning.

Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator.

Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Future Computing Platform Design: A Cross-Layer Design Approach.

Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration.

Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing.

Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, Che-Ching Lin

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.

Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang

IEEE Trans. Computers, 2019

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.

Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li

Proceedings of the 46th International Symposium on Computer Architecture, 2019

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.

Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling.

Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang

CoRR, 2018

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.

Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.

Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang

IEEE Comput. Archit. Lett., 2017

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.

Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016

Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell.

Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches.

Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015

Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference.

Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie

ACM Trans. Design Autom. Electr. Syst., 2015

EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.

Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie

ACM Trans. Archit. Code Optim., 2015

Core vs. uncore: the heart of darkness.

Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.

Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

2010

Memory Latency Reduction via Thread Throttling.

Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010