Hsiang-En Huang

According to our database, Hsiang-En Huang authored at least 5 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS.

Pen-Jui Peng, Po-Lin Lee, Hsiang-En Huang, Wei-Jian Huang, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng

IEEE J. Solid State Circuits, 2022

2021

A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Hsiang-En Huang

IEEE J. Solid State Circuits, 2021

A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS.

Pen-Jui Peng, Hsiang-En Huang, Wei-Chien Huang, Po-Lin Lee, Ming-Wei Lin, Ying-Zong Juang, Sheng-Hsiang Tseng

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2019

A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Sheng-Tsung Lai, Chao-Hsuan Chen, Hsiang-En Huang, Ted Shih

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS.

Pen-Jui Peng, Yan-Ting Chen, Chao-Hsuan Chen, Sheng-Tsung Lai, Hsiang-En Huang, Ho-Hsuan Lu, Tsai-Chin Yu

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018