Hsiang-Chun Cheng
Orcid: 0009-0003-9112-6628
According to our database1,
Hsiang-Chun Cheng
authored at least 8 papers
between 2011 and 2024.
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Bibliography
2024
IEEE J. Solid State Circuits, January, 2024
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2020
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
2012
Reading and Writing Performance in School-aged Children with Specific Language Impairment or/and with Developmental Coordination Disorder Identified at Preschool Age.
Proceedings of the 34th Annual Meeting of the Cognitive Science Society, 2012
2011
Reading and writing performance in 7-8 year old children with developmental coordination disorder identified at 5-6 years old.
Proceedings of the 33th Annual Meeting of the Cognitive Science Society, 2011