Hoyoung Yoo
Orcid: 0000-0001-9323-0398
According to our database1,
Hoyoung Yoo
authored at least 33 papers
between 2011 and 2024.
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Bibliography
2024
Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training.
Sensors, April, 2024
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
2022
IEEE Internet Things J., 2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
Proceedings of the International SoC Design Conference, 2020
2019
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
2018
Resource usage of LTE networks for machine-to-Machine group communications: Modeling and analysis.
Comput. Electr. Eng., 2018
Proceedings of the International SoC Design Conference, 2018
2016
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Commun. Lett., 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
IEEE J. Solid State Circuits, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011