Hoyoung Tang

According to our database, Hoyoung Tang authored at least 13 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology.

Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck

IEEE J. Solid State Circuits, April, 2024

2023

A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.

Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology.

Taejoong Song, Hakchul Jung, Giyoung Yang, Hoyoung Tang, Hayoung Kim, Dongwook Seo, Hoonki Kim, Woojin Rim, Sanghoon Baek, Sangyeop Baeck, Jonghoon Jung

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application.

Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi, Taejoong Song, Jongwook Kye

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability.

Heetak Kim, Hoyoung Tang, Woong Choi, Jongsun Park

IEEE Trans. Biomed. Circuits Syst., 2020

Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates.

Hoyoung Tang, Donghyeon Cho, Dongwoo Lew, Taehwan Kim, Jongsun Park

Neurocomputing, 2020

2019

Spike Counts Based Low Complexity SNN Architecture With Binary Synapse.

Hoyoung Tang, Heetak Kim, Hyeonseong Kim, Jongsun Park

IEEE Trans. Biomed. Circuits Syst., 2019

An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding.

Heetak Kim, Hoyoung Tang, Jongsun Park

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications.

Juseong Lee, Hoyoung Tang, Jongsun Park

IEEE Trans. Circuits Syst. Video Technol., 2018

Spike Counts Based Low Complexity Learning with Binary Synapse.

Hoyoung Tang, Heetak Kim, Donghyeon Cho, Jongsun Park

Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2016

Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors.

Hoyoung Tang, Jongsun Park

IEEE Trans. Very Large Scale Integr. Syst., 2016

Customized SRAM design for low power video code applications.

Sangkyu Lee, Hoyoung Tang, Kyungrak Choi, Jongsun Park

Proceedings of the International SoC Design Conference, 2016

2015

A hybrid multimode BCH encoder architecture for area efficient re-encoding approach.

Hoyoung Tang, Gihoon Jung, Jongsun Park

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015