Hoyeol Cho

According to our database1, Hoyeol Cho authored at least 6 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
0
1
2
1
1
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.
IEEE J. Solid State Circuits, 2016

2015

2014
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.
IEEE J. Solid State Circuits, 2014

2013

2008
Performance comparison between copper, carbon nanotube, and optical interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007


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