Howard C. Luong
Orcid: 0000-0003-1501-9313Affiliations:
- Hong Kong University of Science and Technology (HKUST), Department of Electronic & Computer Engineering, Kowloon, Hong Kong
- University of California, Berkeley, CA, USA (PhD 1994)
According to our database1,
Howard C. Luong
authored at least 125 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For contributions to CMOS radio-frequency transceiver design".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2024
A 10.8-14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration.
IEEE J. Solid State Circuits, May, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Injection-Locking Techniques for CMOS Millimeter-Wave and Terahertz Signal Generation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 1.92GHz-3.84GHz 0.74ps-1.09ps-Jitter Inductor-less Injection-Locked Frequency Synthesizer with Automatic Frequency Selection and Timing Alignment.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
An 8-mW 66-GHz Active Circulator with 40dB TX-RX Isolation in 65nm CMOS for Full-Duplex Radios.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2019
A Multi-Loop-Controlled AC-Coupling Supply Modulator With a Mode-Switching CMOS PA in an EER System With Envelope Shaping.
IEEE J. Solid State Circuits, 2019
An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC.
IEEE J. Solid State Circuits, 2019
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 23-mW 60-GHz Differential Sub-Sampling PLL with an NMOS-Only Differential-Inductively-Tuned VCO.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Design and Analysis of Millimeter-Wave Digitally Controlled Oscillators With C-2C Exponentially Scaling Switched-Capacitor Ladder.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs.
IEEE J. Solid State Circuits, 2017
A 7.9-GHz Transformer-Feedback Quadrature Oscillator With a Noise-Shifting Coupling Network.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
20.3 An 86-to-94.3GHz transmitter with 15.3dBm output power and 9.6% efficiency in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA.
IEEE J. Solid State Circuits, 2015
A dithering-less 54.79-to-63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Passive RFID Tag Embedded Temperature Sensor With Improved Process Spreads Immunity for a -30°C to 60°C Sensing Range.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
2013
Analysis and Design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz Divide-by-4 Injection-Locked Frequency Divider With Harmonic Boosting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
A 4-Path 42.8-to-49.5 GHz LO Generation With Automatic Phase Tuning for 60 GHz Phased-Array Receivers.
IEEE J. Solid State Circuits, 2013
Analysis and Design of a 2.9-mW 53.4-79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
A 0.9GHz-5.8GHz SDR receiver front-end with transformer-based current-gain boosting and 81-dB 3rd-order-harmonic rejection ratio.
Proceedings of the ESSCIRC 2013, 2013
A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011).
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - µm CMOS technology.
Int. J. Circuit Theory Appl., 2012
A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receivers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A WCDMA/WLAN digital polar transmitter with AM replica feedback linearization in 65nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2<sup>nd</sup>-order noise-shaping TDC and a transformer-coupled QVCO.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010).
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs.
IEEE J. Solid State Circuits, 2011
A 0.05-to-10GHz 19-to-22GHz and 38-to-44GHz SDR frequency synthesizer in 0.13μm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE J. Solid State Circuits, 2010
Correction to "A Sub- μ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application" [Jun 10 1246-1255].
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
0.9mW 7GHz and 1.6mW 60GHz frequency dividers with locking-range enhancement in 0.13µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A Double-Balanced Quadrature-Input Quadrature-Output Regenerative Frequency Divider for UWB Synthesizer Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-µm CMOS Process.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection.
IEEE J. Solid State Circuits, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation.
IEEE J. Solid State Circuits, 2005
A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
2004
IEEE J. Solid State Circuits, 2004
2003
A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-μm CMOS process.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the ESSCIRC 2003, 2003
A 1-V 13-mW 2.5-GHz double-rate phase-locked loop with phase alignment for zero delay.
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the ESSCIRC 2003, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-μm CMOS process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection.
IEEE J. Solid State Circuits, 2002
A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique.
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A 0.9-V 0.2-μW CMOS single-opamp-based switched-opamp ΣΔ modulator for pacemaker applications.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
IEEE J. Solid State Circuits, 2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
2-V 900-MHz quadrature coupled LC oscillators with improved amplitude and phase matchings.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A fourth-order CMOS bandpass amplifier with high linearity and high image rejection for GSM receivers.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1997
J. Circuits Syst. Comput., 1997