Houxiang Ji
Orcid: 0009-0008-8402-0127
According to our database1,
Houxiang Ji
authored at least 14 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
Proceedings of the 2023 USENIX Annual Technical Conference, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
2022
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the IEEE International Conference on Big Data, 2022
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors.
CoRR, 2019
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Favorable Block First: A Comprehensive Cache Scheme to Accelerate Partial Stripe Recovery of Triple Disk Failure Tolerant Arrays.
Proceedings of the 46th International Conference on Parallel Processing, 2017