Hou-Jen Ko

According to our database1, Hou-Jen Ko authored at least 7 papers between 2007 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Optimizing data layout and system configuration on FPGA-based heterogeneous platforms.
Proceedings of the International Conference on Computer-Aided Design, 2018

2013
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping.
IEEE Trans. Very Large Scale Integr. Syst., 2013

General data structure expansion for multi-threading.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2013

2012
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2007
A Double-Issue Java Processor Design for Embedded Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


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