Hossein Valavi

According to our database, Hossein Valavi authored at least 13 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing.

Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma

IEEE J. Solid State Circuits, 2022

2021

Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs.

Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing.

Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020

Hardware acceleration to address the costs of data movement

Hossein Valavi

PhD thesis, 2020

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing.

Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma

IEEE J. Solid State Circuits, 2020

The Landscape of Matrix Factorization Revisited.

Hossein Valavi, Sulin Liu, Peter J. Ramadge

CoRR, 2020

Revisiting the Landscape of Matrix Factorization.

Hossein Valavi, Sulin Liu, Peter J. Ramadge

Proceedings of the 23rd International Conference on Artificial Intelligence and Statistics, 2020

2019

A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute.

Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma

IEEE J. Solid State Circuits, 2019

A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing.

Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

Multi-dataset Low-rank Matrix Factorization.

Hossein Valavi, Peter J. Ramadge

Proceedings of the 53rd Annual Conference on Information Sciences and Systems, 2019

2018

A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing.

Hongyang Jia, Yinqi Tang, Hossein Valavi, Jintao Zhang, Naveen Verma

CoRR, 2018

A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement.

Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Upper-Bound on the Required Size of a Neural Network Classifier.

Hossein Valavi, Peter J. Ramadge

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018