Hossam A. H. Fahmy

According to our database1, Hossam A. H. Fahmy authored at least 65 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Novel End-to-End Production-Ready Machine Learning Flow for Nanolithography Modeling and Correction.
Adv. Artif. Intell. Mach. Learn., 2024

2023
Fast Parallel Multiple Access Distributed Arithmetic (FPMA-DA) Reconfigurable FIR Filter.
Proceedings of the International Conference on Microelectronics, 2023

2020
Software and Hardware Implementation Sensitivity of Chaotic Systems and Impact on Encryption Applications.
Circuits Syst. Signal Process., 2020

High-Frequency Memristor-Based BFSK and 8-QAM Demodulators.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019
Two-Dimensional Rotation of Chaotic Attractors: Demonstrative Examples and FPGA Realization.
Circuits Syst. Signal Process., 2019

On Optimization of Mixed-Radix FFT: A Signal Processing Approach.
Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019

A Novel Generic Low Latency Hybrid Architecture for Parallel Pipelined Radix-2<sup>k</sup> Feed Forward FFT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Novel Model for Injecting Error in Probabilistic Gates.
Proceedings of the 31st International Conference on Microelectronics, 2019

2018
Dual Split-Merge: A high throughput router architecture for FPGAs.
Microelectron. J., 2018

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations.
J. Circuits Syst. Comput., 2018

NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA.
Integr., 2018

Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources.
Integr., 2018

Modified CONNECT: New Bufferless Router for NoC-Based FPGAs.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Low Energy ASIC Design for Main Memory Data Compression/Decompression.
Proceedings of the 30th International Conference on Microelectronics, 2018

2017
Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit.
IEEE Trans. Computers, 2017

Low energy pipelined Dual Base (decimal/binary) Multiplier, DBM, design.
Microelectron. J., 2017

Adaptive and optimum multiport readout of non-gated crossbar memory arrays.
Microelectron. J., 2017

Non-volatile low-power crossbar memcapacitor-based memory.
Microelectron. J., 2017

Generalized Smooth Transition Map Between Tent and Logistic Maps.
Int. J. Bifurc. Chaos, 2017

Finite Precision Logistic Map between Computational Efficiency and Accuracy with Encryption Applications.
Complex., 2017

Exploiting the Dynamic Partial Reconfiguration on NoC-Based FPGA.
Proceedings of the New Generation of CAS, 2017

Chaotic systems based on jerk equation and discrete maps with scaling parameters.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Radix-4 successive cancellation decoding of polar codes with partial sum lookahead.
Proceedings of the 29th International Conference on Microelectronics, 2017

Efficient GPU utilization in heterogeneous big data cluster using token-based scheduler.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
What are the Correct Results for the Special Values of the Operands of the Power Operation?
ACM Trans. Math. Softw., 2016

Memristor based BPSK and QPSK demodulators with nonlinear dopant drift model.
Microelectron. J., 2016

Design guidelines for embeded NoCs on FPGAs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Design guidelines for soft implementations to embedded NoCs of FPGAs.
Proceedings of the 11th International Design & Test Symposium, 2016

Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation.
Proceedings of the 11th International Design & Test Symposium, 2016

Double-sided bifurcations in tent maps: Analysis and applications.
Proceedings of the 3rd International Conference on Advances in Computational Tools for Engineering Applications, 2016

2015
Fair memory access scheduling algorithms for multicore processors.
Int. J. Parallel Emergent Distributed Syst., 2015

Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Adaptive Time-Based Least Memory Intensive Scheduling.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Generalized chaotic maps and elementary functions between analysis and implementation.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Binary floating point verification using random test vector generation based on SV constraints.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGA.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Two-stage optimization of CORDIC-friendly FFT.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Speeding-up fast fourier transform.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Real-Time Memory Controller for Embedded Multi-core System.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014
Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Two Extended Programmable BCH Soft Decoders Using Least Reliable Bits Reprocessing.
Circuits Syst. Signal Process., 2014

Corrected and accurate Verilog-A for linear dopant drift model of memristors.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Time-Based Least Memory Intensive Scheduling.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

NoC-based many-core processor using CUSPARC architecture.
Proceedings of the 26th International Conference on Microelectronics, 2014

Verification of the decimal floating-point square root operation.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Memristor-based memory: The sneak paths problem and solutions.
Microelectron. J., 2013

Two programmable BCH soft decoders for high rate codes with large word length.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Low energy high speed reed-solomon decoder using two parallel modified evaluator Inversionless Berlekamp-Massey.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Implementation and Evaluation of Large Interconnection Routers for Future Many-core Networks on Chip.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

High Performance Memory Requests Scheduling Technique for Multicore Processors.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Residue codes for error correction in a combined decimal/binary redundant floating point adder.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
A Precise High-Level Power Consumption Model for Embedded Systems Software.
EURASIP J. Embed. Syst., 2011

A reconfigurable baseband processor for wireless OFDM synchronization sub-system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Memory conflict analysis for a multi-standard, reconfigurable turbo decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Verification of decimal floating-point fused-multiply-add operation.
Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

Efficient decimal leading zero anticipator designs.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
Energy and Delay Improvement via Decimal Floating Point Units.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
A decimal fully parallel and pipelined floating point multiplier.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

Power estimation methodology for VLIW Digital Signal Processors.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

Bipolar sequences correlator and squarer for multiple-access systems.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2006
Algorithmic truncation of minimax polynomial coefficients.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Redundant Adders Consume Less Energy.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A novel covalent redundant binary Booth encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
The Case for a Redundant Format in Floating Point Arithmetic.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003


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