Hortensia Mecha
Orcid: 0000-0002-9774-4609
According to our database1,
Hortensia Mecha
authored at least 29 papers
between 1994 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles.
Microprocess. Microsystems, February, 2023
2022
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories.
IEEE Access, 2022
2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
2018
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
IET Comput. Digit. Tech., 2018
2016
Neurocomputing, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2010
A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
2008
Allocation heuristics and defragmentation measures for reconfigurable systems management.
Integr., 2008
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays.
IET Comput. Digit. Tech., 2008
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Resource Management for Hw Multitasking in Three Dimensional FPGAs.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
FPGA Resource Management Using Internal RAM as Aata Cache.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2004
Proceedings of the Field Programmable Logic and Application, 2004
2003
Microelectron. J., 2003
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.
Proceedings of the Integrated Circuit and System Design, 2003
1999
1998
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1994
Microprocess. Microprogramming, 1994