Hoosung Cho
According to our database1,
Hoosung Cho
authored at least 2 papers
between 2008 and 2009.
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Bibliography
2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009
2008
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008