Hooman Farkhani
Orcid: 0000-0002-8632-2240
According to our database1,
Hooman Farkhani
authored at least 27 papers
between 2008 and 2024.
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Bibliography
2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
2023
Energy-Efficient Spintronic-Based Neuromorphic Computing System Using Current Mode Track and Termination Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
2021
Flexible Energy-Efficient Implementation of Adaptive Spiking Encoder for Neuromorphic Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain Implants.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Low-Noise High Input Impedance Analog Front-End Design for Neural Recording Implant.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
2018
A Low-Power High-Speed Spintronics-Based Neuromorphic Computing System Using Real-Time Tracking Method.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2015
Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Microelectron. J., 2014
A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology.
Microelectron. J., 2014
Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008