Hongzhuo Liu
Orcid: 0009-0001-2180-2606
According to our database1,
Hongzhuo Liu
authored at least 9 papers
between 2022 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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2023
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique.
IEEE J. Solid State Circuits, August, 2024
IEEE J. Solid State Circuits, July, 2024
An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN<sub>div</sub>.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022