Hongyu Chen

Affiliations:
  • University of California, San Diego, La Jolla, CA, USA


According to our database1, Hongyu Chen authored at least 21 papers between 2001 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Legend:

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Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2011
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2007
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Communication latency aware low power NoC synthesis.
Proceedings of the 43rd Design Automation Conference, 2006

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Unified quadratic programming approach for mixed mode placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Improving the efficiency of static timing analysis with false paths.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A multi-level transmission line network approach for multi-giga hertz clock distribution.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A multiple level network approach for clock skew minimization with process variations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Optimal planning for mesh-based power distribution.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Floorplan representations: Complexity and connections.
ACM Trans. Design Autom. Electr. Syst., 2003

Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

An algebraic multigrid solver for analytical placement with layout based clustering.
Proceedings of the 40th Design Automation Conference, 2003

The Y-architecture: yet another on-chip interconnect solution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Physical Planning Of On-Chip Interconnect Architectures.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Revisiting floorplan representations.
Proceedings of the 2001 International Symposium on Physical Design, 2001


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