Hongxiang Fan

Orcid: 0000-0003-2387-5611

According to our database1, Hongxiang Fan authored at least 49 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Design of Fully Spectral CNNs for Efficient FPGA-Based Acceleration.
IEEE Trans. Neural Networks Learn. Syst., June, 2024

Low Latency Variational Autoencoder on FPGAs.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2024

LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics.
ACM Trans. Embed. Comput. Syst., March, 2024

Progressive Mixed-Precision Decoding for Efficient LLM Inference.
CoRR, 2024

Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA.
CoRR, 2024

Hardware-Aware Parallel Prompt Decoding for Memory-Efficient Acceleration of LLM Inference.
CoRR, 2024

SAE: Single Architecture Ensemble Neural Networks.
CoRR, 2024

Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Breaking Physical and Linguistic Borders: Multilingual Federated Prompt Tuning for Low-Resource Languages.
Proceedings of the Twelfth International Conference on Learning Representations, 2024

Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point.
IEEE Trans. Neural Networks Learn. Syst., August, 2023

Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic.
IEEE Trans. Computers, June, 2023

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA.
CoRR, 2023

Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations.
IEEE Trans. Parallel Distributed Syst., 2022

Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs.
IEEE Trans. Neural Networks Learn. Syst., 2022

FPGA-Based Acceleration for Bayesian Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors.
CoRR, 2022

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Customizable FPGA-based Accelerator for Binarized Graph Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Optimizing quantum circuit placement via machine learning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks.
CoRR, 2021

ComBiNet: Compact Convolutional Bayesian Neural Network for Image Segmentation.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

Quantum Most-Significant Digit-First Addition.
Proceedings of the 12th International Green and Sustainable Computing Workshops, 2021

Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

High-Performance FPGA-based Accelerator for Bayesian Neural Networks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Mapping Large LSTMs to FPGAs with Weight Reuse.
J. Signal Process. Syst., 2020

VINNAS: Variational Inference-based Neural Network Architecture Search.
CoRR, 2020

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Optimizing Reconfigurable Recurrent Neural Networks.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2018

Memory-Efficient Architecture for Accelerating Generative Networks on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
F-C3D: FPGA-based 3-dimensional convolutional neural network.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
IC security evaluation against fault injection attack based on FPGA emulation.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016


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